1. Field of the Invention
The present invention relates generally to a branch predictor, system and method of branch prediction, and more particularly, to a branch predictor, system and method of branch prediction with a reduced power consumption in pipelined microprocessors.
2. Description of the Related Art
By the conventional art, microprocessors may include a pipeline architecture. The performance of pipelined microprocessors may relate to their use of branch prediction. Pipelined microprocessors may execute instructions sequentially or may skip certain sequential instructions in order to execute instructions in a non-sequential order. A non-sequential execution of instructions may be referred to as a branch, and the instruction indicating to the pipelined microprocessors to execute a branch may be referred to as a branch instruction. In pipelined microprocessors, a branch may be a factor in determining the overall performance of a microprocessor because the microprocessor may stall its execution until a determination is made on whether or not to execute the branch.
A branch predictor may be used to predict the next instruction address to be executed by the pipelined microprocessors. The predicted next instruction address may be fetched from a branch target buffer in order to avoid a pipeline stall. However, an error in the branch prediction may result in a pipeline stall, as the correct next instruction address may need to be read into the branch target buffer. Thus, branch prediction may affect the overall performance of the microprocessor.
Various branch predictors have been suggested by the conventional art. For example, a GSHARE branch predictor may predict a branch by using a branch prediction table indexed by an address of the current instruction being executed and a history of previous branch results. Hereinafter, the history of previous branch results may be referred to as a global history.
FIG. 1 illustrates a block diagram of a branch prediction system using the conventional GSHARE branch predictor. Referring to FIG. 1, the conventional branch prediction system may include a processor core 102, a branch predictor 104 and a branch target buffer 106. The processor core 102 may output an address ADDR of the current instruction to the branch predictor 104, and fetch the address of the next branch from the branch target buffer 106. The branch predictor 104 may perform branch prediction for the current instruction address and may transfer a final branch prediction value PRED_V to the processor core 102.
FIG. 2 illustrates a block diagram of the conventional GSHARE branch predictor of FIG. 1 in more detail. Referring to FIG. 2, the conventional GSHARE branch predictor may index an entry 204-k of a branch prediction table 204 using an index value IND_V generated by an XOR operation 206 performed on an output of a global history 202 and a current instruction address 200. A least significant bit (LSB) of the value stored in the indexed entry 204-k (i.e. a result of a previous branch for an instruction) may be selected as the final branch prediction value PRED_V of the current instruction address 200. Thus, branch prediction may be performed irrespective of whether or not a branch of the current instruction address is taken. If such a branch prediction is completed, the final branch prediction value PRED_V may be used to update the global history 202 and the entry 204-k of the branch prediction table 204 in order to predict a next branch in a next iteration of the branch prediction.
Referring again to FIG. 1, because the branch prediction for the current instruction address and the fetching of the branch address from the branch target buffer 106 may be performed in a single clock cycle, the processor core 102 may access both the branch prediction table 204 of FIG. 2 and the branch target buffer 106 of FIG. 1 prior to determining whether to execute a branch based on the current instruction address. However, if the branch prediction result PRED_V indicates a branch will not be taken, it may not be necessary to fetch a branch address from the branch target buffer 106. Fetching an unnecessary branch address from the branch target buffer 106 may increase the power consumption of the pipelined microprocessors.